Hi Guys,
Some progress on the ECU.
The CPU is up and running with a small Real Time Kernel.
The four pulsed input channels have been implemented using one of the 32 bit timers. The edge on which the timer capture happens is programmable, so right now I'm just using a spare timer to drive the inputs for both front and rear coil secondary inputs. One captures on the rising edge and the other on the falling edge. Frequency and pulse width measurement is made to one micro-Sec.
The internal AtoD is a 12 bit SAR type with with 18 possible inputs. By the time I allocated all the pins needed for coil drivers, injector drivers, etc., there were 11 pins left for use as analog inputs. Right now I am measuring 11 external pins and two internal signals, core CPU Temp, and internal reference voltage. The AtoD is running in batch acquisition mode with all channels sampled and summed 8 times, shifted right 2 bits (so as to leave a rounding bit) and then dumped to memory via a DMA channel. The DMA terminal count ISR sums the new readings to four groups of readings. Each secondary ignition capture generates an interrupt which grabs the group with the most samples, copies it to a working group, and then zeros that group. Anyway, that gives me an average of the AtoD readings over the last two revolutions of the engine. I may change strategy during testing, but that's the plan for now.
Two output bits have been allocated to verify/test timing.
The pics below shows timing bit #1, timing bit #2, and one edge of the "engine" timer. Timing bit #1 is toggled by the "idle" task. Any gap in toggling means either an ISR or a higher priority task is executing. In this pic Timing bit #2 is toggled at the beginning and end of the AtoD DMA terminal count ISR.
Looking at timing bit #1 you can see the AtoD DMA terminal count ISR, the Kernel timer tick ISR every mSec (along with the tasks triggered by the timer tick), and the input capture ISR (and the input capture task) generated by edge on trace #3. At present the input capture ISR just stores the captured value and signals the input capture task. In the future it will also output pulses for ignition and fuel injection. As you can see, the CPU is very lightly loaded at present.
The input capture task buffers the captured reading in a 30 reading circular buffer, calculates the period of the last revolution, the RPMS based on that period, and an RPM based on 0.3 second gate time (for display). This task also scales all of the AtoD readings to engineering units for use in calculating pulse width and phase for output.
I also bought the evaluation board for an ASIC (Application Specific Integrated Circuit) which targets 4 cylinder engine engine control. The ASIC provides a CAN bus driver, power for the CPU, two five volt outputs for sensor excitation, four injector drives, four pre-drives for the IGBTs that drive the ignition coils, and a lot of outputs that will go unused.
Up next is pulse generation followed by bringing up the Arinc 825 bus for communication with the control head.
Forever Forward,
Wes